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SerDes
 

MoSys’ silicon proven PHYs support a wide range of protocols ranging from 1.25Gbps to 11.3Gbps. Chip designers get access to risk-free silicon-proven PHYs at advanced process nodes.

MoSys offers a broad portfolio of silicon-proven PHYs across a wide range of protocols and process nodes.

Silicon-proven PHYs

Key Benefits

  • Silicon validated designs that ensure lowest risk
  • Extremely low jitter – exceeds SONET requirements
  • High jitter tolerance
  • Proven interoperability with industry standard link layers
  • FlipChip and Wirebond ready designs
  • Best-in-class testability
    • Multiple loop-back modes
    • IEEE 1149.6
    • Internal Eye Monitor
    • Built-In PRBS Generator & Checker

Protocols Supported

  • CEI-11, 10G KR, OC-192
  • XAUI, RXAUI
  • PCI Express 2.0, SATA
  • OC-48, SGMII, SRIO, CPRI
  • Please contact MoSys for all other protocols

Availability

  • TSMC 40G
  • TSMC 40LP
  • TSMC 65LP
  • Fujitsu 65HP
  • Please contact MoSys for all other process variants

Click here for a complete listing of MoSys IP: 


Our Applications


  • NetworkingConsumer/GraphicsComputingStorage
Our Applications MoSys in Networking
The explosive demand for internet bandwidth is driving the need for next generation network systems. These systems require significantly more...

Our Applications MoSys in Computing
Improved performance and the trend towards multi-core computing is driving the need for next generation high end computing systems...

Our Applications MoSys in Consumer/Graphics
MoSys differentiated and patented 1T-SRAM embedded memory IP enables next generation networking SoCs to have 3 times the density in the same...
Our Applications MoSys in Storage
The dramatic explosion in information within the enterprise across the extended network in high end storage systems, and the need to have...